View L9634_8986611.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/36 L9634 october 2004 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. 1 features eight squib deployment drivers deployment current and time programmable via spi, (1.2a/2ms and 1.75a/4ms) capability to deploy with 1.47a (2.14a) under 40v (21v) load-dump condition and the low side mos shorted to -1v. 5.5mhz spi interface with message validation 4 channels of discrete/serial logic arming interface programmable via spi deployment driver self- diagnostics: ? short to battery/ground and open circuit ? squib resistance measurement ? short between channels detec- tions ? high and low side mos tests ? ground loss detection -40 c to +85 c operating ambient temperature 4kv esd capability on all output- driver pins and 2kv on all others 2 description the L9634 is an octal intelligent squib driver asic. it is packaged in a 44pin thin quad flat pack (tqfp) package and designed using st's proprietary bcd4 technology. the uh30 is intend- ed to deploy up to eight airbag squib circuits and provide diagnostics for each of the deployment drivers. each of the eight drivers is sized to deliver up to 1.75a minimum for up to 4ms. the deploy- ment current and time are both programmable via the spi port preliminary data octal intelligent squib driver asic rev. 1 fi gure 1. p ac k age table 1. order codes part number package L9634 tqfp44 tqfp44 obsolete product(s) - obsolete product(s)
L9634 2/36 figure 2. block diagram miso sclk mosi cs iref test/ depen vrmeas vdd sqh0 sql0 vres0 sqh1 sql1 vres1 sqh5 sql5 vres5 sqh4 sql4 vres4 sqh2 sql2 l s d h s d vres2 isense isense diagnostic sqh3 sql3 l s d h s d vres3 isense isense diagnostic sqh7 sql7 l s d h s d vres7 isense isense diagnostic sqh6 sql6 l s d h s d vres6 isense isense discrete / serial mode diagnostic l s d h s d isense isense diagnostic l s d h s d isense isense diagnostic l s d h s d isense isense diagnostic l s d h s d isense isense diagnostic gnd2 gnd0 gnd3 gnd0 gnd0 gnd6 gnd0 gnd7 gnd0 gnd1 gnd0 gnd4 gnd0 gnd5 gnd0 arm01/ armin arm23/ armen arm45/ armclk arm67/ armout por gnd0 s p i logic + adc discrete / serial mode discrete / serial mode discrete / serial mode obsolete product(s) - obsolete product(s)
3/36 L9634 figure 3. pin connection (top view) table 2. pin function n pin description i/o type 1 sqh0 high side driver output for channel 0 out 2 sql0 low side driver output for channel 0 out 3 gnd0 power ground 0 - 4 armclk arm serial mode clock input in arm45 discrete arm signal for channel 4 & 5 in 5 armout arm serial mode data output out arm67 discrete arm signal for channel 6 & 7 in 6 armen arm serial mode data enable in arm23 discrete arm signal for channel 2 & 3 in 7 armin arm serial mode data input in arm01 discrete arm signal for channel 0 & 1 in 8 test test input pin in depen deployment enable in 9 gnd7 power ground 7 - 10 sql7 low side driver output for channel 7 out 11 sqh7 high side driver output for channel 7 out 12 vres7 reserve voltage for loop channel 7 in 13 vres6 reserve voltage for loop channel 6 in 14 sqh6 high side driver output for channel 6 out 15 sql6 low side driver output for channel 6 out 16 gnd6 power ground 6 - 17 cs spi chip select in d04at523 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 armen / arm23 armout / arm67 armclk / arm45 sql0 sqh0 gnd0 sqh7 sql7 gnd7 armin / arm01 test / depen vres7 vres6 sqh6 sql6 cs gnd6 gnd5 sql5 sqh5 vres5 vres4 vres0 vres1 sqh1 sql1 vrmeas gnd1 gnd2 sql2 sqh2 vres2 vres3 miso vdd iref sql4 sqh4 gnd4 sqh3 sql3 gnd3 mosi sclk 12 13 14 15 16 obsolete product(s) - obsolete product(s)
L9634 4/36 table 3. absolute maximum ratings *) *) maximum ratings are absolute values: exceeding any one of these values may cause permanent damage to the integrated circuit. table 4. thermal data 18 gnd5 power ground 5 - 19 sql5 low side driver output for channel 5 out 20 sqh5 high side driver output for channel 5 out 21 vres5 reserve voltage for loop channel 5 in 22 vres4 reserve voltage for loop channel 4 in 23 sqh4 high side driver output for channel 4 out 24 sql4 low side driver output for channel 4 out 25 gnd4 power ground 4 - 26 iref external current reference resistor out 27 vdd vdd supply voltage in 28 miso spi data out out 29 mosi spi data in in 30 sclk spi clock in 31 gnd3 power ground 3 - 32 sql3 low side driver output for channel 3 out 33 sqh3 high side driver output for channel 3 out 34 vres3 reserve voltage for loop channel 3 in 35 vres2 reserve voltage for loop channel 2 in 36 sqh2 high side driver output for channel 2 out 37 sql2 low side driver output for channel 2 out 38 gnd2 power ground 2 - 39 vrmeas supply voltage for resistance measurement in 40 gnd1 power ground 1 - 41 sql1 low side driver output for channel 1 out 42 sqh1 high side driver output for channel 1 out 43 vres1 reserve voltage for loop channel 1 in 44 vres0 reserve voltage for loop channel 0 in symbol parameter value unit v dd supply voltage -0.3 to 6.5 v vrmeas voltage -0.3 to 40 v vres voltage -0.3 to 40 v sqhx, sqlx squib high and low side drv -1 to 40 v v in discrete input voltage -0.3 to 6.5 v t j maximum junction temperature +150 c symbol parameter value unit r thj-amb thermal resistance junction to ambient 68 c/w r thj-case thermal resistance junction to case 14 c/w t stg storage temperature -50 to +175 c table 2. pin function (continued) n pin description i/o type obsolete product(s) - obsolete product(s)
5/36 L9634 3 electrical characteristics table 5. electrical characteristics (vres = 6.5 to 40v, vdd = 4.9 to 5.1v, vrmeas = 7.0v to 26.5v, t amb = -40c to +95c unless otherwise specified) symbol parameter test condition min. typ. max. unit v rst vdd internal voltage reset vdd drops until deployment drivers are disabled 4.2 4.7 v i dd vdd input current normal operation 5 ma short to ?1v on sqh 5 short to ?1v on sql 5 deployment 20 v ih input voltage mosi, sclk, cs, armx input logic = 1 2.0 v v il input logic = 0 0.8 v hys 50 mv i lkg input leakage current mosi, sclk v in = vdd 1 a v in = 0 to v ih -1 v ih_depen depen input voltage 2.0 v v il_depen 0.8 v hys 50 mv v ih_test test input voltage 8.5 v v il_test 5.5 i pd input pulldown current armx, cs v in = v il to vdd 10 50 a depen v in = v il to vdd 10 100 v oh output voltage miso i oh = -800 avdd? 0.8 v v ol i ol = 1.6ma 0.4 i z miso tri-state current miso = vdd 10 a miso = 0v -10 deployment drivers dc specification i lkg sqh leakage vrmeas=vdd=0, vresx=36v, v sqh = 0v 50 a i stg vrmeas=18v; vdd=5v; v sqh = -1v -5 ma i lkg vresx bias current 1 vrmeas=18v; vdd=5v; vresx=36v;sqh shorted to sql 10 a i lkg sql leakage vrmeas=vdd=0, v sql =18v -10 10 a i stg vrmeas=18v; vdd=5v; v sql = -1v -5 ma i stb vrmeas=18v; vdd=5v; v sql = 18v 5ma i pd sql pulldown current v sqlx = 1.8v - vdd 500 700 a sg th short to ground threshold vdd = 5.0v 1.9 2.1 v sb th short to battery threshold vdd = 5.0v 3.9 4.1 v obsolete product(s) - obsolete product(s)
L9634 6/36 oc th open circuit threshold vdd = 5.0v 1.9 2.1 v v i_th mos test load voltage detection 100 300 mv i src resistance measurement current source vdd = 5.0v; vrmeas = 7.0v to 26.5v 38 42 ma i sink resistance measurement current sink 45 55 ma r dson total high and low side on resistance high side mos + low side mos vres = 6.9v; i = 1.2a @95 c 1.5 ? r dson total high and low side on resistance high side mos + low side mos vres = 6.9v; i vres = 1.1a @95 c 1.5 ? r dson high side mos on resistance vres = 40v; i vres = 1.1a; ta = 9 5 c 0.50 ? r dson low side mos on resistance vres = 40v; i vres = 1.1a; ta = 9 5 c 1.0 ? i deploy deployment current (channel 0, 3, 4, and 7) mosi: command mode d11=0; r load =3.75 ? ; vres=6.9 to 40v 1.2 1.47 a mosi: command mode d11=1; r load =5.3 ? ; vres=12v to 21v 1.75 2.14 i lim low side mos current limit (channel 0, 3, 4, and 7) mosi: command mode d11=1/ 0; r load =5.3 ? ; v sqh =18v 1.75 2.14 a i deploy deployment current (channel 1, 2, 5, and 6) mosi: command mode d11=0; r load =3.75 ? ; vres=6.9 to 40v 1.34 1.64 a mosi: command mode d11=1; r load =5.3 ? ; vres=12v to 21v 1.95 2.39 i lim low side mos current limit (channel 1, 2, 5, and 6) mosi: command mode d11=1/ 0; r load =5.3 ? ; v sqh =18v 1.95 2.39 a i bias diagnostics bias current v sqh =0v; part is configured to run in diagnostics mode via spi -7 -4 i pd v bias diagnostics bias voltage i sqh = -1.5ma 2.7 3.3 v r iref iref resistance threshold open circuit 62.5 k ? short circuit 2.5 k ? r l_range load resistance range %0000 0000 = 0.0 ? ; %1111 1111 = 10.0 ? 0.0 10.0 w adc acc adc accuracy r l = 4.0 ? to 10.0 ? 5% r l = 0.0 ? to 4.0 ? 5 counts adc res adc resolution 8 bits i peak mos transient response peak current see figure 19 and figure 20 2.0 i final table 5. electrical characteristics (continued) (vres = 6.5 to 40v, vdd = 4.9 to 5.1v, vrmeas = 7.0v to 26.5v, t amb = -40c to +95c unless otherwise specified) symbol parameter test condition min. typ. max. unit obsolete product(s) - obsolete product(s)
7/36 L9634 1. not applicable during the diagnostic. figure 4. mos settling time and turn-on time 1 deployment drivers ac specification t por por de-glitch timer 5 20 s t on moss turn on time armx and depen pins asserted measured from falling edge cs to 90% of i final ; see figure 19 and figure 20 150 s t settle moss settling time armx and depen pins asserted measured from falling edge cs to 90% - 110% of i final ; see figure 19 and figure 20 300 s t pulse pulse stretch timer see ?pulse stretch timer table? 0 60 ms table 5. electrical characteristics (continued) (vres = 6.5 to 40v, vdd = 4.9 to 5.1v, vrmeas = 7.0v to 26.5v, t amb = -40c to +95c unless otherwise specified) symbol parameter test condition min. typ. max. unit obsolete product(s) - obsolete product(s)
L9634 8/36 figure 5. mos settling time and turn-on time 2 2. application information only; not tested. 3. time from falling edge of cs until spi ?diagnostic? flag is set. table 5. electrical characteristics symbol parameter test condition min. typ. max. unit t p_acc pulse stretch timer accuracy -20 20 % t glitch pulse stretcher de-glitch timer 5 25 s t deploy deployment time vres = 6.9 - 40v 2 ; (see table) 22.25ms vres = 12 ? 21v 3 ; (see table) 44.5 t timeout diagnostic bias current time time from falling edge of cs until spi diagnostic complete flag is set, in case of short to gnd for a single channel diagnostic. 2.5 ms t flt_dly fault detection filter 2 10 50 s i slew rmeas current di/dt 40 ma/ s t res resistance measurement time 2 duration when i diag_src and i diag_sink are connected to sqh and sql during a resistance measurement 2.5 ms t mos_on mos test turn-on time 2 on-time of a ls/hs driver during a mos test 2.5 ms t detect mos test detection window 2 time window to check for a ls/ hs mos fault on a single loop 7.5 ms t prop_dly ls/hs mos turn off propagation delay 2 time is measured from the valid ls/hs mos condition to the ls/ hs turn off 10 s t diag1 diagnostic time 3 for a single loop; mos test disabled 5ms t diag_mult for 8 loops mos tests disabled 40 obsolete product(s) - obsolete product(s)
9/36 L9634 notes: 1. parameters t dis and t ho is measured with no additional capacitive load beyond the normal test fixture capacitance on the miso pin. additional capacitance during the disable time test erroneously extends the measured output disable time, and minimum capaci- tance on miso is the worst case for output hold time. figure 6. spi timing diagram table 6. spi timing (all spi timing is performed with a 200pf load on miso unless otherwise noted) item symbol parameter limits min max unit - fop transfer frequency dc 5.50 mhz 1t sck sclk period 181 - ns 2t lead enable lead time 65 - ns 3t lag enable lag time 50 - ns 4t sclkhs sclk high time 65 - ns 5t sclkls sclk low time 65 - ns 6t sus mosi input setup time 20 - ns 7t hs mosi input hold time 20 - ns 8t a miso access time - 66 ns 9t dis miso disable time (note 1) - 100 ns 10 t vs miso output valid time - 45 ns 11 t ho miso output hold time (note 1) 0 - ns 12 t ro rise time (design information) - 30 ns 13 t fo fall time (design information) - 30 ns 14 t csn cs negated time 100 - ns obsolete product(s) - obsolete product(s)
L9634 10/36 table 7. arming serial mode timing (all arming serial mode timing is performed with a 50pf load on armout unless otherwise noted) figure 7. arming serial mode timing item symbol parameter limits min max unit - fop transfer frequency dc 2 mhz 1t armclk armclk period 500 ns 2t lead enable lead time 250 ns 3t lag enable lag time 100 ns 4t armclk_hs armclk high time 220 ns 5t armclk_ls armclk low time 220 ns 6t sus armin input setup time 30 ns 7t hs armin input hold time 10 ns 8t a armout access time 125 ns 9t vs armout output valid time 190 ns 10 t ho armout output hold time 10 ns 11 t ro rise time (design information) 30 ns 12 t fo fall time (design information) 30 ns 13 t armen_n armen negated time 200 ns obsolete product(s) - obsolete product(s)
11/36 L9634 4 circuit description osd is an integrated circuit to be used in air bag systems. its main functions are deployment of the air bag and diagnostics of the sdm (sensing deployment module). the osd supports 8 de-ployment loops. the main features of osd ic are: 8 deployment drivers sized to deliver 1.2a min for 2ms min at 40v max or 1.75a min for 4ms min at 21v max (current and time are internally limited while power supply is externally lim-ited). 10% accuracy for deployment current. 5% accuracy for deployment time. high side and low side current limits programmable via spi. low-voltage internal reset 5.5mhz spi interface spi message validation 4 discrete logic arming inputs high and low-side mos tests squib resistance measurement with 5% accuracy short to -1v protection on all deployment loops (high and low side). capability to deploy with 1.2a min under 40v load-dump condition and the low side mos is shorted to -1v. capability to deploy with 1.75a min under 21v condition and the low side mos is shorted to -1v capability to deploy with 1.75a min, when the high side mos is shorted to 18v-battery and -1v ground difference. capability to deploy the air bag with 1.2a min @ 6.9v vres deployment loops short to ground and short to battery detection short between loops detection -40c to +95c ambient temperature package: 44ld tqfp technology: st's proprietary bcd4 process 4.1 power on reset vdd loss of regulation detection is filtered for tpor prior to issue an internal reset. this filter is intended to provide protection from short transients on vdd input. when vdd input voltage decreases below vrst for tpor, osd undergoes an internal reset. osd keeps all current sinks and current sources, except the ipd, inactive and all outputs are driven to an inactive state and remains inactive as vdd decays down to 0v. when vdd rises above vrst, the outputs and the internal current sinks and current sources are en- abled. when osd is in reset, none of the outputs are momentarily turned on. 4.2 deployment drivers the on chip deployment drivers are sized to deliver ideploy. deployment current and period are pro- grammable via spi. the high side driver survives deployment condition 1 and 2 as defined here below. sqlx is shorted to ground (-1v) in these two conditions. table 8. deployment survivability conditions no. drivers conditions i deploy voltage r load duration 1. sqhx 1.47a vresx = 40v; sqlx = -1v 1.7 ? 2.5ms 2. 2.14a vresx = 21v; sqlx = -1v 1.7 ? 4.5ms 3. sqlx 2.14a sqhx = 18v 1.7 ? 4.5ms obsolete product(s) - obsolete product(s)
L9634 12/36 the low side driver survives deployment condition 3 as defined above. upon receiving a valid deployment condition, the respective sqh and sql drivers are turned on. also, sqh and sql drivers are turned on momentarily during a mos diagnostic. otherwise, sqh and sql are inactive under any normal, fault, or transient conditions. upon a successful deployment of the respective sqh and sql drivers, a deploy command success flag is asserted via spi. refer to figure 4, figure 5, figure 6, and figure 7. for the valid deployment condition and the "deploy command success" timing. the following power-up conditions are considered as normal operations in osd. vres input can be con- nected to either a power supply output or an ignition voltage. vdd is connected to the 5v output of power supply. when vres is connected to the power supply, vdd voltage will reach its regulation voltage before vres voltage is stabilized. in this condition, osd has a control of its internal logic and prevents an inad- vertent turn-on of the drivers. when vres is connected to the ignition, vres voltage will be stabilized before vdd reach its regulation voltage. in this condition, all drivers are inactive. a pulldown on the gates of high side drivers (sqh) is provided to prevent these drivers from momentarily turning-on. any fault conditions on osd does not turn on the sqh and sql drivers. only a valid deployment condition turns on the respective sqh and sql drivers. 4.3 arming inputs the arming inputs serve as a fail-safe mechanism to prevent inadvertent deployment. along with the spi deployment bit, these inputs provide redundancy. these pins are used either as discrete outputs or as a serial data communication interface with 4-bit shift register. pulse stretch timer is provided for each chan- nel/loop. either armx signal or spi deployment bit starts the pulse stretcher. figure 8. arming serial mode diagram when a valid deployment command is sent through the spi, the pulse stretcher is initiated immediately following the falling edge of cs. when another valid deployment command is sent before the timer for the first command expired, the timer is refreshed. sending an idle command terminates the pulse stretch timer operation. only a timer operation started by a valid spi deployment command is terminated. an idle com- mand does not affect the timer operation started by arm signal. osd deploys a channel, only when the respective arm signal is asserted during a valid pulse stretcher signal. during the deployment, osd turns on the respective high (sqh) and low side (sql) drivers for tdeploy. once deployment is initiated it can not be terminated. if one or more channels are deploying, osd ignores all commands to the respective channels. the rest of the channels resume operation and respond to the spi commands. refer to figure 5 for a deployment diagram initiated by a spi deployment command. in a discrete mode, when the arm signal is asserted (active high), the pulse stretcher signal is asserted after the de-glitch filter time, tglitch, expires. the de-glitch filter is used to prevent noise from starting the pulse stretcher. the pulse stretcher timer, tpulse, is initiated after a de-glitch time of the arm falling edge. osd deploys a channel, only when the respective spi deployment command is sent during a valid pulse stretcher signal. during the deployment, osd turns on the respective high (sqh) and low side (sql) drivers for tdeploy. when deployment is initiated it can not be stopped. refer to figure 4 and figure 5 for a deployment diagram initiated by an arm discrete signal. in serial mode, osd latch the arm state for each channel from the shift register when armen is negated. after the de-glitch filter time, tglitch, of the armen falling edge expires, osd starts the pulse stretch timer for the respective channel. serial mode is selected by setting bit d5 in the deployment configuration register 1 (see "deployment configuration register 1 table 15"). osd deploys a channel, only when the respective spi deployment command is sent during a valid pulse stretcher signal. during the deploy- arm45/armclk arm67/armout arm23/armen msb lsb arm01/armin spi shift register spi.config1reg.d5 obsolete product(s) - obsolete product(s)
13/36 L9634 ment, osd turns on the respective high (sqhx) and low side (sqlx) drivers for tdeploy. when deploy- ment is initiated it can not be stopped. refer to figure 11 and figure 12 for a deployment diagram initiated by an arming signal in serial mode. figure 9. discrete mode: deployment sequence with pulse stretch timer enabled figure 10. discrete mode: deployment se quence with pulse stretch timer disabled t pulse pulse stretch timer 2 ms or 4ms deploy valid deployment window spi cs deploy success flag 1: spi deploy command 2: clear deploy success flag spi cs notes: 11 2 t pulse 2 ms or 4ms t pulse valid deployment window 1 12 valid deployment window t < t pulse valid deployment window t pulse 1 3 3: spi idle command t pulse 3 armx status flag de-glitch armen notes: a: arming enable b: arming disable depen input is assumed to be active in this sequence. arm_cmp deploy status flag t pulse t pulse pulse stretch timer de-glitch deploy spi cs deploy success flag valid deployment window t pulse 1 spi cs notes: valid deployment window 1 2 ms or 4ms t < t pulse 1 2 t pulse 2 ms or 4ms valid deployment window 112 valid depl oyment window 3 1: spi deploy command 2: clear deploy success flag 3: spi idle command 3 t < t pulse armx status flag depen input is assumed to be active in this sequence. arm_cmp deploy status flag obsolete product(s) - obsolete product(s)
L9634 14/36 figure 11. serial mode: deployment sequence with pulse stretch timer enabled figure 12. serial mode: deployment sequence with pulse stretch timer disabled 4.4 arm01 / armin in discrete mode, this pin acts as the arm input channel 0 and channel 1. in serial mode, this pin acts as the input of arming shift register. the armin input takes data from the processor or another osd while armen is asserted. the msb is the first bit of each word received on armin. the lsb is the last bit of each word received on armin. see figure 8 below for aming shift register. this pin has a ttl level compatible input voltages allowing proper operation with another devices using a 3.3v to 5.0v supply. t pulse pulse stretch timer 2 ms or 4ms deploy valid deployment window spi cs deploy success flag 1: spi deploy command 2: clear deploy success flag spi cs notes: 1 1 2 t pulse 2 ms or 4ms t pulse valid deployment window 1 1 2 valid deployment window t < t pulse valid deployment window t pulse 1 3 3: spi idle command t pulse 3 armx status flag armen a b a b a b a b a b armen notes: a: arming enable b: arming disable depen input is assumed to be active in this sequence. de-glitch deploy status flag t pulse t pulse obsolete product(s) - obsolete product(s)
15/36 L9634 figure 13. arming shift register 4.5 arm23 / armen in discrete mode, this pin acts as the arm input channel 2 and channel 3. in serial mode, this pin acts as an active high input to select this device for serial transfers. this pin has a ttl level compatible input volt- ages allowing proper operation with another devices using a 3.3v to 5.0v supply. while armen is asserted, arming register data is shifted into the armin pin and shifted-out of the ar- mout pin on both rising and falling edges of armclk. on the falling edge of armen, osd latch-in the bits from the shift register, and clear the shift register contents. 4.6 arm45 / armclk in discrete mode, this pin acts as the arm input channel 4 and channel 5. in serial mode, this pin acts as a clock input for serial communication. this pin has a ttl level compatible input voltages allowing proper operation with another devices using a 3.3v to 5.0v supply. when armen is asserted, on the rising or falling edge of armclk the logic level input at the armin pin is shifted into the internal arming shift register. while msb in the shift register is shifted-out on the ar- mout pin. serial data is shifted in and out of the shift register on each armclk edge. when armen is negated, osd ignores armclk signal. a clock edge counter is provided to verify a valid serial arming communication. a valid serial arming com- munication contains (4n - 1) armclk edges. otherwise, osd ignores the serial arming messages. 4.7 arm67 / armout in discrete mode, this pin acts as the arm input channel 6 and channel 7. in serial mode, this pin acts as the output of arming shift register. this pin has a ttl level compatible input voltages allowing proper op- eration with another devices using a 3.3v to 5.0v supply. when armen is negated, armout pin is pulled down. when armen is asserted, the msb is the first bit of the nibble shifted onto armout. the lsb is the last bit shifted onto armout. 4.8 test / depen (deployment enable) depen is a deployment enable input, which is an active high input. when depen is negated, it inhibits the high-side and the low-side moss from turning on. if depen is negated when a valid deployment is received, osd inhibits the deployment. if depen is negated when a diagnostic command is received, osd executes the diagnostic sequence. if a mos diagnostic is executed while depen is negated, osd returns a low-side mos fault. spi remains functional while this pin is pulled low. when this pin is asserted, osd is able to drive its high and low side drivers upon receiving a valid deployment command or a mos diagnostic. depen does not initiate a deployment nor terminate a deployment if it is already started. to enter a test mode, this pin has to be pulled higher than vih_test. 4.9 deployment driver diagnostics osd runs an on-chip self-diagnostics when commanded via spi. by default, osd is in the monitor mode (d15 & d14 = %11). the on-chip diagnostic operates according to the flow chart shown in figure 15. if a fault condition is detected, the state machine asserts a fault bit, which serves as a flag to the processor. once a fault bit asserted, osd terminates the diagnostic tests for that particular channel and start diag- nostic tests on the next channel. the fault information in osd is sent out through miso. for diagnostic arm67 arm01 arm23 arm45 msb lsb 14 3 2 obsolete product(s) - obsolete product(s)
L9634 16/36 mode spi bit definition. osd is able to differentiate short to battery, open circuit, and short to ground. a resistance measurement provides the resistance value of a load connected between sqh and sql. mos diagnostic verifies the functionality of the high and low side mos. refer to figure 14 for the diagnostic diagram. a detailed op- eration for each test is described in sections below. figure 14. diagnostic diagram figure 15. diagnostic flow chart diagnostics s1 a/d converter data registers 8 to 1 mux s0 s2 spi sclk cs miso mosi sqlx sg th sqhx i src vign i sink vresx i bias v bias sb th oc th i pd gndx gnd0 monitor mode run on-chip diagnostic no short to ground yes resistance measurement indicate short to ground yes no fet test enabled no yes indicate no fault ls fet failed yes no indicate ls fet failed hs fet failed yes no indicate hs fet failed low side driver fet test high side driver fet test indicate open circuit open circuit yes no indicate short to battery short to battery yes no obsolete product(s) - obsolete product(s)
17/36 L9634 4.10 short between loops diagnostic osd has a loop bias voltage that is multiplexed between the eight deployment loops. the bias voltage is pulled-up to vdiag_bias. each deployment loop is pulled to ground through a current sink, ipd. if one of these loops is shorted to the one that is biased, a "short between loops" fault bit is asserted and re- ported via spi. refer to figure 16 for short between loops diagram. short between loops test is initiated when osd receives one of the following message: mosi monitor mode message with bit d12 = '1,' bit d9 = '1,' and bit d8 = '1.' mosi diagnostic mode message with bit d12 = '1' and bit d9 = '1.' the test terminates when osd receives one of the following message: mosi monitor mode message with bit d12 = '1,' bit d9 = '1,' and bit d8 = '0' mosi diagnostic mode message with bit d12 = '1' and bit d9 = '0.' mosi command mode with bit d7 through bit d0 = '0.' if the test is in progress, osd will continue the test when any of the following messages is received: mosi monitor mode, except the one with bit d12 = '1,' bit d9 = '1,' and bit d8 = '0' mosi register mode figure 16. short between loops diagram after a por event, short between loop is disabled. need to receive a spi command to execute a short between loop diagnostic. 4.11 short to battery diagnostic during a short to battery test, a current source referenced to vdd is connected to the sqhx. when no short to battery condition exists, sqhx and sqlx are equal to vdiag_bias. if the voltage on sqhx is above sbth for tflt_dly, osd will assert the short to battery fault. refer to figure 17 for a short to battery test diagram. sql0 sg th sb th sqh0 vres0 sql1-7 sg th sqh1-7 vres1-7 diagnostics off off off off i pd i bias i pd gnd0 gnd0 gnd0 gnd1-7 v bias sb th obsolete product(s) - obsolete product(s)
L9634 18/36 figure 17. short-to-battery diagnostic diagram 4.12 open circuit and short to ground diagnostic during an open circuit or a short to ground test, a current source referenced to v diag_bias is connected to the sqhx. when no open circuit or short to ground condition exists, sqhx and sqlx are equal to v diag_bias . an open circuit fault is detected when sqhx voltage is at v diag_bias and the sqlx voltage is at ground potential. a short to ground is detected when sqlx voltage is at ground potential and the sqhx voltage is below the open circuit threshold, oc th . figure 18. open circuit and short to ground diagnostic diagram the open circuit and short to ground conditions are summarized in the table below. a fault condition exists for at least t flt_dly before osd sets the respective fault bit. table 9. open circuit / short to ground fault condition 4.13 resistance measurement in a resistance measurement test, osd provides a current source, isrc, on sqhx and a current sink, isink, on sqlx. the 8-bit adc is multiplexed between the deployment loops. this adc converts the volt- age across the sqhx and sqlx. the conversion results is stored for spi retrieval. figure 19 shows the resistance measurement diagram. comparator output condition oc sg 00 invalid state 0 1 short to ground 1 0 normal operation 1 1 open circuit sb th diagnostics sqlx sqhx vresx off off i pd gnd0 gndx i bias v bias diagnostics sqlx sqhx vresx off off sg th oc th i pd gnd0 gndx i bias v bias obsolete product(s) - obsolete product(s)
19/36 L9634 figure 19. resistance measurement diagram the adc has a resolution of 8 bits and an accuracy of 5%. the adc is robust to disruption that may occur due to adjacent loops short to 40v or -1v. 4.14 mos diagnostic during a mos test, the i bias current source referenced to v bias is connected to the sqhx. in case of nor- mal condition, sqhx and sqlx are equal to v bias . depen pin is asserted in order to run a mos diagnostic. if depen pin is negated, osd will inhibit the high/low side mos from turning on. in this case, the mos diagnostic is terminated after t detect is expired and the respective mos fault bit is set. 4.15 low side mos diagnostic upon detection of the following conditions, osd turns the low side driver off and terminates the diagnostic within the specified time, tprop_dly. v sql is less than sgth threshold voltage (v sqhx - v sqlx ) is greater than v i_th v sqh is greater than sb th threshold voltage any of the above conditions are considered as a normal operation. upon detection any of these conditions, osd does not set the low side driver fault bits. on a single channel, high-side and low-side mos diagnostics is completed within t detect . a low-side mos fault bit is only set when t detect is expired before any of the above conditions are detected. a fault detection filter, t flt_dly , is provided to protect against short-transients on sqh and sql pins. see figure 20 for mos test diagram. figure 20. mos diagnostic diagram sqlx sqhx i src vign i sink i pd vresx off to adc off gnd0 gndx sqlx sg th sb th sqhx vresx hs gate drive diagnostics ls gate drive i pd gndx gnd0 i bias v bias obsolete product(s) - obsolete product(s)
L9634 20/36 4.16 high side mos diagnostic upon detection of the following conditions, osd turns the high side driver off and terminate the diagnostic within the specified time, t prop_dly . v sqh is greater than sbth threshold voltage (v sqhx - v sqlx ) is greater than v i_th v sql is less than sg th threshold voltage any of the above conditions are considered as a normal operation. upon detection any of these conditions, osd does not set the high side driver fault bits. on a single channel, high-side and low-side mos diagnostics are completed within t detect . a high-side mos fault bit is only set when t detect is expired before any of the above conditions are detected. a fault detection filter, t flt_dly , is provided to protect against short-transients on sqh and sql pins. see figure 20 for mos test diagram. 4.17 loss of ground diagnostic loss of ground is detected when the power ground of a deployment loop has a high impedance/open con- nection to the ground. each channel has a dedicated power ground and a dedicated loss of ground detec- tion. upon a detection of loss of ground condition, osd inhibits a diagnostic and a deployment for the respective channel. the rest of the channels are not affected by a loss of ground condition on the other channels. a loss of ground condition does not affect a deployment or a pulse strech timer that is already started. a ground reference for osd logic is connected to gnd0 pin. when osd detects a high impedance on this ground reference, osd will go in reset mode. 4.18 serial peripheral interface (spi) the osd contains a serial peripheral interface consisting of serial clock (sclk), serial data out (miso), serial data in (mosi), and chip select (cs). this device is configured as an spi slave. figure 21. spi block diagram 4.19 chip select (cs) the cs input selects osd for serial data transfers. this ttl-compatible input has an internal pull-down to command the de-asserted state should an open circuit condition occur when cs is asserted, the miso pin is released from tri-state mode, and all status information is latched in the spi shift register. while cs is asserted, register data is shifted in the mosi pin and shifted out the miso pin on each subsequent sclk. when cs is negated, the miso pin is tri-stated and the fault register reloaded (latched) with the current filtered status data. to allow sufficient time to reload the fault registers; the cs pin must remain negated for at least t csn . cs must also be immune to spurious pulses as defined in the spi timing table (miso may come out of tri- state, but no status bits can be cleared and no control bits altered). glitches on the cs line while sclk is not running will be ignored, although the miso pin may be enabled. in each valid cs, osd allows 16-bit miso msb lsb control bits status bits input shift register sclk mosi cs output shift register cs vdd vss 30 a obsolete product(s) - obsolete product(s)
21/36 L9634 spi transfer. osd ignores all spi transfers, which are not a 16-bit transfer and issue a spi fault response in the next valid cs. 4.20 serial clock (sclk) the sclk input is the clock signal input for synchronization of serial data transfer. this pin has ttl level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. when cs is asserted, both the spi master and this device latch input data on the rising edge of sclk. the spi master typically shifts data out on the falling edge of sclk, as does this device. 4.21 serial data output (miso) the miso output pin is in a tri-state condition when cs is negated. when cs is asserted, the msb is the first bit of the word transmitted on miso and the lsb is the last bit of the word transmitted on miso. this pin supplies a "rail to rail" output, so if interfaced to a microprocessor that is using a lower vdd supply, the appropriate microprocessor input pin shall not sink more than ioh and shall not clamp the miso volt- age to less than v oh(min) while the miso pin is in a logic "1" state. 4.22 serial data input (mosi) the mosi input takes data from the master microprocessor while cs is asserted. the msb is the first bit of each word received on mosi and the lsb is the last bit of each word received on mosi. this pin has ttl level compatible input voltages allowing proper operation with micro-processors using a 3.3 to 5.0 volt supply. 4.23 spi transmission the spi provides access to read/write to the registers internal to osd. osd responses to various com- mands summarized in the below table. osd response to the previous command is sent in the next valid cs. table 10. osd spi response 4.24 spi bit definition - mosi bit figure 22. mosi bit layout table 11. mosi mode bits definition mode bits mosi command mode bits miso response d15 d14 d15 d14 0 0 register mode 0 0 register mode 0 1 command mode 0 1 command mode 1 0 diagnostic mode 1 1 status response 1 1 monitor mode 1 1 status response x x spi transmission fault 1 0 spi fault response bit d15 bit d14 description 0 0 register mode 0 1 command mode 1 0 diagnostic mode 1 1 monitor mode d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb obsolete product(s) - obsolete product(s)
L9634 22/36 4.25 register mode register mode message is defined as shown in table below. table 12. mosi register mode message definition when bit d13 is set to '1,' osd writes the data-bit to its internal register. the address bit desig-nates a specific register in osd. this address-bit is defined as shown below. when the adc resistance measurement is addressed, osd ignores the data-bit. upon the detection of this adc resistance measurement on the address-bit, osd sends the 8-bit resistance measurement value in the register mode response. a write request contains valid mode bits, bit d13 set to '1,' valid address bits and valid data bits. in the next valid cs, a register mode response contains the valid register content and not the echo from previous command. a read request contains valid mode bits, bit d13 set to '0,' and valid address bits. the data bits will be ignored by the osd. in the next valid cs, a register mode response contains a valid register content. this register is determined by the address bits sent in the previous command. bit state description d15 0 mode bits d14 0 d13 0 read configuration register 1 write configuration register d12 address-bit d11 d10 d9 d8 d7 data-bit d6 d5 d4 d3 d2 d1 d0 table 13. address-bit definition bit d12 bit d11 bit d10 bit d9 bit d8 description res adc diag ad1 ad0 program other options 0 0 0 0 0 status.flt configuration register 0 0 0 0 1 deployment configuration 1 register 0 0 0 1 0 deployment configuration 2 register 00011soft reset res adc diag ad1 ad0 diagnostic fault registers 0 0 1 0 0 channel 0 and 1 register (see table 18) 0 0 1 0 1 channel 2 and 3 register, table 19 0 0 1 1 0 channel 4 and 5 register (see table 20) obsolete product(s) - obsolete product(s)
23/36 L9634 4.26 status.flt configuration register status.flt register is defined as shown in the below table. the setting of these registers will influence the diagnostic fault indication flag in the status response. if any of these bits set to '1,' osd inhibits the faults of the respective channels from affecting bit d13 (diagnostic fault flag) in the miso status re- sponse. this status.flt configuration register does not afftect the operation of diagnostic fault regis- ters. table 14. status.flt configuration register bit d12 bit d11 bit d10 bit d9 bit d8 description 0 0 1 1 1 channel 6 and 7 register, table 21 res adc ad2 ad1 ad0 adc resistance measurement result 0 1 0 0 0 8-bit adc measurement register: ch 0 0 1 0 0 1 8-bit adc measurement register: ch 1 0 1 0 1 0 8-bit adc measurement register: ch 2 0 1 0 1 1 8-bit adc measurement register: ch 3 0 1 1 0 0 8-bit adc measurement register: ch 4 0 1 1 0 1 8-bit adc measurement register: ch 5 0 1 1 1 0 8-bit adc measurement register: ch 6 0 1 1 1 1 8-bit adc measurement register: ch 7 bit status description d7 0 enable fault report on channel 7 (default) 1 disable fault report on channel 7 d6 0 enable fault report on channel 6 (default) 1 disable fault report on channel 6 d5 0 enable fault report on channel 5 (default) 1 disable fault report on channel 5 d4 0 enable fault report on channel 4 (default) 1 disable fault report on channel 4 d3 0 enable fault report on channel 3 (default) 1 disable fault report on channel 3 d2 0 enable fault report on channel 2 (default) 1 disable fault report on channel 2 d1 0 enable fault report on channel 1 (default) 1 disable fault report on channel 1 d0 0 enable fault report on channel 0 (default) 1 disable fault report on channel 0 table 13. address-bit definition (continued) obsolete product(s) - obsolete product(s)
L9634 24/36 4.27 deployment configuration register 1 the deployment configuration register 1 is defined as shown in the next table. during a deployment event, a write request to this register is inhibited. table 15. deployment configuration register 1 bit d3 through bit d0 is used to inhibit the armx signal from initiating the pulse stretch timer. when these bits are "0," armx signal is prohibited from initiating the timer. otherwise, a valid armx signal starts the timer. if the timer has already initiated by the spi deployment command, the armx signal does not affect the timer. bit d7 and bit d6 is used to set the period of pulse stretch timer. osd has 8 independent timers for each channel. either a valid armx or a spi deployment command is capable to start the pulse stretch timer. these bits set the timer duration according to table. these values are default to %00 after battery connect. table 16. pulse stretch timer bit status description d7 pulse stretch timer (see table) d6 d5 0 arm parallel mode (default) 1 arm serial mode d4 - don?t care d3 0 arm67 pulse stretch disable (default) 1 arm67 pulse stretch enable d2 0 arm45 pulse stretch disable (default) 1 arm45 pulse stretch enable d1 0 arm23 pulse stretch disable (default) 1 arm23 pulse stretch enable d0 0 arm01 pulse stretch disable (default) 1 arm01 pulse stretch enable bit d7 bit d6 stretch period (ms) 00 7.5 01 15 10 30 11 60 obsolete product(s) - obsolete product(s)
25/36 L9634 4.28 deployment configuration register 2 the second deployment configuration register contains bits to configure the deployment period and the deployment current for each loop. during a deployment event, a write request to this register is inhibited. the register is defined as shown in herebelow table. table 17. deployment configuration register 2 4.29 soft reset the soft reset in osd is achieved by writing $aa and $55 within two subsequent 16-bit spi transmissions. if the sequence is broken, the processor will be required to re-transmit the sequence. osd is not in reset if the sequence is not completed within two subsequent 16-bit spi transmissions. 4.30 diagnostic fault registers these diagnostic fault registers contain the fault status for each of the channels. each register is cleared immediately after a spi reading on that particular register. the diagnostic fault registers is defined as shown here below: table 18. diagnostic fault register: channel 0 and 1 bit status description d7 0 channel 6/7 2ms deployment period (default) 1 channel 6/7 4ms deployment period d6 0 channel 6/7 1.2a deployment current (default) 1 channel 6/7 1.75a deployment current d5 0 channel 4/5 2ms deployment period (default) 1 channel 4/5 4ms deployment period d4 0 channel 4/5 1.2a deployment current (default) 1 channel 4/5 1.75a deployment current d3 0 channel 2/3 2ms deployment period (default) 1 channel 2/3 4ms deployment period d2 0 channel 2/3 1.2a deployment current (default) 1 channel 2/3 1.75a deployment current d1 0 channel 0/1 2ms deployment period (default) 1 channel 0/1 4ms deployment period d0 0 channel 0/1 1.2a deployment current (default) 1 channel 0/1 1.75a deployment current bit state description d7 0 no fault: channel 1 1 fault exists: channel 1 d6 channel 1 diagnostic fault-bit refer to diagnostic fault-bit definition table 22 d5 d4 d3 0 no fault: channel 0 1 fault exists: channel 0 d2 channel 0 diagnostic fault-bit refer to diagnostic fault-bit definition table 22 obsolete product(s) - obsolete product(s)
L9634 26/36 table 19. diagnostic fault register: channel 2 and 3 table 20. diagnostic fault register: channel 4 and 5 table 21. diagnostic fault register: channel 2 and 3 diagnostic fault bit indicates short between loops, short to battery, open circuit, short to ground, high or low side mos fault. the channel number is determined by the address bit in register mode command. these faults are decoded as shown in diagnostic fault-bit definition table. bit d7 and bit d3 indicate if a fault condition exists in the respective channels. loss of ground fault has the highest priority among all fault conditions. bit state description d7 0 no fault: channel 3 1 fault exists: channel 3 d6 channel 3 diagnostic fault-bit refer to diagnostic fault-bit definition table 22 d5 d4 d3 0 no fault: channel 2 1 fault exists: channel 2 d2 channel 2 diagnostic fault-bit refer to diagnostic fault-bit definition table 22 bit state description d7 0 no fault: channel 5 1 fault exists: channel 5 d6 channel 5 diagnostic fault-bit refer to diagnostic fault-bit definition table 22 d5 d4 d3 0 no fault: channel 4 1 fault exists: channel 4 d2 channel 4 diagnostic fault-bit refer to diagnostic fault-bit definition table 22 bit state description d7 0 no fault: channel 7 1 fault exists: channel 7 d6 channel 7 diagnostic fault-bit refer to diagnostic fault-bit definition table 22 d5 d4 d3 0 no fault: channel 6 1 fault exists: channel 6 d2 channel 6 diagnostic fault-bit refer to diagnostic fault-bit definition table 22 obsolete product(s) - obsolete product(s)
27/36 L9634 table 22. diagnostic fault-bit definition 4.31 resistance measurement registers osd has 8 independent resistance measurement registers. the resistance measurement registers is de- fined as shown in the table. table 23. adc resistance measurement register adc resistance measurement registers contain the measurement results of each of the osd deployment channels. the channel number is determined by the address bit in diagnostic command (see address bit definition table 13) d6/d2 d5/d1 d4/d0 description 0 0 0 no fault 0 0 1 short between loops 0 1 0 short to battery 0 1 1 open fault 1 0 0 short to ground 101low side mos fault 1 1 0 high side mos fault 1 1 1 loss of ground fault bit description d7 8-bit adc resistance measurement result d6 d5 d4 d3 d2 d1 d0 obsolete product(s) - obsolete product(s)
L9634 28/36 4.32 command mode command mode message is defined as shown in next table. table 24. mosi command mode message definition odd parity check includes all 16 bits. "don't care" bit is included in the parity check as well. bit d7 to bit d0 is used to start the deployment or the pulse stretch timer. osd provides an independent timer for each channel. when any of these bits are set to '1,' osd starts the deployment of the pulse stretch timer for the respective channels. if any of these bits are set to '0' when the pulse stretch timer is still active, osd terminates the pulse stretch timer for the respective channels. once deployment is initi- ated it will not be terminated. during the deployment, osd will ignore all commands. when depen is negated, osd ignores the deploy command. in other words, osd will not initiate the pulse stretch timer or a deployment in this condition. however, when the pulse stretcher is already started by a deploy command, depen will not terminate the pulse stretch timer. upon receiving an idle command, osd will terminates the pulse stretch timer regardless of depen signal. in this case, only a pulse stretch timer that is started by a deploy command that can be terminated by sending an idle command. bit state description d15 0 mode bits d14 1 d13 odd parity d12 - don?t care d11 - don?t care d10 - don?t care d9 - don?t care d8 - don?t care d7 0 channel 7 idle 1 deploy channel 7 d6 0 channel 6 idle 1 deploy channel 6 d5 0 channel 5 idle 1 deploy channel 5 d4 0 channel 4 idle 1 deploy channel 4 d3 0 channel 3 idle 1 deploy channel 3 d2 0 channel 2 idle 1 deploy channel 2 d1 0 channel 1 idle 1 deploy channel 1 d0 0 channel 0 idle 1 deploy channel 0 obsolete product(s) - obsolete product(s)
29/36 L9634 4.33 diagnostic mode diagnostic mode message is defined as shown in table. table 25. mosi diagnostic mode message definition odd parity check includes all 16 bits. "don't care" bit is included in the parity check as well. when bit d12 is set to '1,' osd starts its internal diagnostics on any channels selected in bit d7 through bit d0. when any of bit d7 through bit d0 are set to '1,' osd performs diagnostics on the respective chan- nels. the diagnostic sequence is shown in figure 10. when bit d12 is set to '0,' osd ignores bit d9 through bit d0. bit d9 and bit d8 are utilized to control the short between loops and mos tests. if any of these bits are set to '1,' osd performs the respective tests to any channels as selected in bit d7 thorugh bit d0. osd exe- cutes these tests based on the diagnostic flow chart, shown in figure 15. bit state description d15 1 mode bits d14 0 d13 odd parity d12 0 read status response only 1 run on-chip diagnostic d11 - don?t care d10 - don?t care d9 0 short between loops test disable 1 short between loops test enable d8 0 mos test disable 1 mos test enable d7 0 disable channel 7 diagnostic 1 enable channel 7 diagnostic d6 0 disable channel 6 diagnostic 1 enable channel 6 diagnostic d5 0 disable channel 5 diagnostic 1 enable channel 5 diagnostic d4 0 disable channel 4 diagnostic 1 enable channel 4 diagnostic d3 0 disable channel 3 diagnostic 1 enable channel 3 diagnostic d2 0 disable channel 2 diagnostic 1 enable channel 2 diagnostic d1 0 disable channel 1 diagnostic 1 enable channel 1 diagnostic d0 0 disable channel 0 diagnostic 1 enable channel 0 diagnostic obsolete product(s) - obsolete product(s)
L9634 30/36 4.34 monitor mode monitor mode message is defined as shown in below: table 26. mosi monitor mode message definition odd parity check includes all 16 bits. "don't care" bit is included in the parity check as well. when bit d12 is set to a '0,' osd ignores all command bits, specified in bit d9 to bit d0. the monitor mode message is allowed to start or to stop the short between loops test. to start the test, both bit d9 and bit d8 has to be set to '1.' to stop the test, bit d9 is set to '1' and bit d8 is set to '0.' if bit d9 is set to '0,' osd ignores the state of bit d8. in this condition, osd does not affect the test. if bit d12 is set to '0,' osd ignores bit d9 and bit d8. bit d7 through bit d0 is used to clear/keep the deploy success flag. when these bits are set to '1,' the flag is cleared. otherwise, osd does not affect the state of these flags. bit state description d15 1 mode bits d14 1 d13 odd parity d12 0 read status response only 1 write commands d11 - don?t care d10 - don?t care d9 0 do not modify short between loops test 1 modify short between loops test d8 0 disable short between loops test 1 enable short between loops test d7 0 keep deploy success flag channel 7 1 clear deploy success flag channel 7 d6 0 keep deploy success flag channel 6 1 clear deploy success flag channel 6 d5 0 keep deploy success flag channel 5 1 clear deploy success flag channel 5 d4 0 keep deploy success flag channel 4 1 clear deploy success flag channel 4 d3 0 keep deploy success flag channel 3 1 clear deploy success flag channel 3 d2 0 keep deploy success flag channel 2 1 clear deploy success flag channel 2 d1 0 keep deploy success flag channel 1 1 clear deploy success flag channel 1 d0 0 keep deploy success flag channel 0 1 clear deploy success flag channel 0 obsolete product(s) - obsolete product(s)
31/36 L9634 4.35 miso bit definition figure 23. miso bit layout table 27. miso mode bits definition 4.36 register mode response register mode response is defined as shown in table. table 28. miso register mode response definition bit d13 is used to reflect the status of mosi read/write bit (refer to bit d13 in "mosi register mode mes- sage definition table"). bit d7 through bit d0 contain data bits. these data bits contain either diagnostic fault register or adc re- sistance measurement register depending upon the mosi request. both register are defined as shown in "diagnostic fault register channel 0 and 1 table" and "adc resistance measurement register table". bit d15 bit d14 description 0 0 register mode response 0 1 command mode response 1 0 spi fault response 1 1 status response bit state description d15 0 mode bits d14 0 d13 echo of mosi read/write bit d12 address bits refer to address-bit definition table d11 d10 d9 d8 d7 data bits d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb obsolete product(s) - obsolete product(s)
L9634 32/36 4.37 command mode response command mode response defined as shown below. table 29. miso command mode response definition depen status flag indicates the state of depen pin. armx status flag indicates the state of the respective armx signal, including the pulse stretch timer. if the pulse stretch timer is initiated by a deployment command, it does not assert the armx status flag. this flag is de/asserted as soon as the de-glitch timer is expired. deploy status flag indicates the spi deployment status for the respective channel. these flags reflect bit d7 through bit d0 of the most recent spi command mode message. these bits do not include the status of pulse stretch timer. these bits will be overwritten by the most recent spi command mode message. when depen is negated, a valid deploy command is ignored and deploy status flag is not set. 4.38 spi fault response this spi fault response indicates a fault in the last mosi transmission. osd uses the parity bit to deter- mine the integrity of the mosi command transmission.this response is defined as shown in table. table 30. miso spi fault response bit state description d15 0 mode bits d14 1 d13 - don?t care d12 0 depen negated 1 depen asserted d11 0 arm67 negated 1arm67 asserted d10 0 arm45 negated 1arm45 asserted d9 0 arm23 negated 1arm23 asserted d8 0 arm01 negated 1arm01 asserted d7 deploy channel 7 status d6 deploy channel 6 status d5 deploy channel 5 status d4 deploy channel 4 status d3 deploy channel 3 status d2 deploy channel 2 status d1 deploy channel 1 status d0 deploy channel 0 status bit state description d15 1 mode bits d14 0 d13 ? d0 don?t care obsolete product(s) - obsolete product(s)
33/36 L9634 4.39 status response status response is the default response to the processor, and is defined as shown in table table 31. miso status response definition diagnostic fault indication flag indicates if a fault exists during the on-chip diagnostic. this bit reports the fault status on channel/s enabled in the status.flt configuration register. diagnostic completion status flag indicates if the on-chip diagnostic is completed. this flag will be set when all the requested channels finish the diagnostic sequence (see figure 15). this flag does not include the status of "short between loops" test. armx status flag indicates the state of the respective armx signal, including the pulse stretch timer. if the pulse stretch timer is initiated by a deployment command, it does not assert the armx status flag. this flag is de/asserted as soon as the de-glitch timer is expired. deploy command success bit indicates if the corresponding channel has finished its deployment se- quence. this bit is set when deployment period, 2ms or 4ms, has expired. once this bit is set, it inhibits the subsequent deployment command until osd receives a spi command to clear this deployment suc- cess flag. refer to figure 9, figure 10, figure 11, and figure 12 for the operation of deployment success flag. bit state description d15 1 mode bits d14 1 d13 0 no diagnostic fault 1 diagnostic fault exists d12 0 diagnostic not complete 1 diagnostic complete / not started d11 0 arm67 negated 1arm67 asserted d10 0 arm45 negated 1arm45 asserted d9 0 arm23 negated 1arm23 asserted d8 0 arm01 negated 1arm01 asserted d7 0 no deployment event: channel 7 1 deploy command successful: channel 7 d6 0 no deployment event: channel 6 1 deploy command successful: channel 6 d5 0 no deployment event: channel 5 1 deploy command successful: channel 5 d4 0 no deployment event: channel 4 1 deploy command successful: channel 4 d3 0 no deployment event: channel 3 1 deploy command successful: channel 3 d2 0 no deployment event: channel 2 1 deploy command successful: channel 2 d1 0 no deployment event: channel 1 1 deploy command successful: channel 1 d0 0 no deployment event: channel 0 1 deploy command successful: channel 0 obsolete product(s) - obsolete product(s)
L9634 34/36 figure 24. tqfp44 (10x10x1.4mm) mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 8.00 0.315 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 8.00 0.315 e 0.80 0.031 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0?(min.), 3.5?(typ.), 7?(max.) tqfp44 (10 x 10 x 1.4mm) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e1 e d1 d e 1 k b tqfp4410 l 0.10mm .004 0076922 d obsolete product(s) - obsolete product(s)
35/36 L9634 table 32. revision history date revision description of changes october 2004 1 first issue obsolete product(s) - obsolete product(s)
information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 36/36 L9634 obsolete product(s) - obsolete product(s)

▲Up To Search▲

Price & Availability of L9634

	To Download L9634 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .